paul h
Supporting Actor
- Joined
- Mar 14, 1999
- Messages
- 544
posted on gamerfeed..
PSP CCU core:
MIPS R4000 32-Bit core
128 bits bus
1~333 MHz @ 1.2V
8 MT main storage (OD RAM)
bus Bandwidth: 2.6 GB/sec
i-Cache/D-Cache
FPU, VFPU (Vector unit): @ 2.6 GFlops
3D-CG Extended Instructions
PSP Media engine:
MIPS R4000 32-Bit core
128 bits bus
1~333 MHz @ 1.2V
Sub MEMORY: 2MB (OD RAM) @ 2.5 GB/sec
i-Cache/D-Cache
90nm CMOS
PSP sound core:
Reconfigurable DSPs
128 bits bus
166 MHz @ 1.2V
5 Giga operation/sec
CODECS
3D sound, Multi Channel
Synthesizer, Effecter
"Sony had claimed that the PSP would have one 32-bit MIPS R4000 CPU at E3 last year. Sony has now claimed that they will run two 32-bit MIPS R4000 CPUs instead. The handheld will also feature an Embedded Wireless LAN 802.1.
The button layout is said to be the same as the Sony trademarked layout, featuring the triangle, circle, square, and x buttons. The games are also said to be controlled with an analog stick."
PSP CCU core:
MIPS R4000 32-Bit core
128 bits bus
1~333 MHz @ 1.2V
8 MT main storage (OD RAM)
bus Bandwidth: 2.6 GB/sec
i-Cache/D-Cache
FPU, VFPU (Vector unit): @ 2.6 GFlops
3D-CG Extended Instructions
PSP Media engine:
MIPS R4000 32-Bit core
128 bits bus
1~333 MHz @ 1.2V
Sub MEMORY: 2MB (OD RAM) @ 2.5 GB/sec
i-Cache/D-Cache
90nm CMOS
PSP sound core:
Reconfigurable DSPs
128 bits bus
166 MHz @ 1.2V
5 Giga operation/sec
CODECS
3D sound, Multi Channel
Synthesizer, Effecter
"Sony had claimed that the PSP would have one 32-bit MIPS R4000 CPU at E3 last year. Sony has now claimed that they will run two 32-bit MIPS R4000 CPUs instead. The handheld will also feature an Embedded Wireless LAN 802.1.
The button layout is said to be the same as the Sony trademarked layout, featuring the triangle, circle, square, and x buttons. The games are also said to be controlled with an analog stick."